1. Field of the Invention
The present invention relates to a semiconductor storage device, and more particularly, to a semiconductor storage device that may perform a die sort test for a memory cell.
2. Description of the Related Art
The semiconductor manufacturing process generally has a die sort test for a semiconductor chip when the chip is still a bare chip before packaging, the test being to check the chip's various properties and functions and the like. The die sort test is performed on the chips after they are diced, and also on the chips before they are diced, i.e., when they are on the semiconductor wafer.
It is required to reduce the test time of the die sort test on the chips on the semiconductor wafer. This is done by, for example, a group of chips formed on the wafer being probed collectively (see, for example, JP 2002-33360 (paragraphs [0002] to [0007] and the like)).
In the collective probing, fewer pins of each chip allow more chips to be tested at the same time, thus reducing the test time. Accordingly, compressing the input and output data from a plurality of data lines in each chip is performed to use fewer input/output pads than the data lines to input/output the test data (data compression).
It is difficult, however, to apply the data compression to a semiconductor storage device that may store parity data for error correction. Specifically, when the data compression is applied to the memory area for the parity data and the memory area for the normal data in the same way, the normal data and the parity data for error correction of the normal data cannot be read as being related to each other. Thus, it is difficult to decide whether redundancy rescue should be conducted or not.